Design of LDPC Decoder Using FPGA: Review of Flexibility

Low Density Parity Check (LDPC) codes have become very popular now-a-days because of their shannon limit approaching error correcting capability and hence have been used in many applications. This paper demonstrates a flexible Low Density Parity Check (LDPC) decoder which is an improve ment over other existing work on a general LDPC decoder. In this paper we have presented a fully flexible LDPC decoder design in FPGA which supports different codes and data rates. This decoder finds application in many communication standards such as Wireless LAN (IEEE 802.lln), WIMAX (IEEE 801.16e) and DVB-S2, on a single hardware platform which makes the transition from theory to practice a much easier one. Finally, this paper proposes a method of designing of fully flexible LDPC Decoder in Spartan6xc6slx16-3 FPGA hardware.